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1 industrial temperature range IDT5T2010 2.5v zero delay pll clock driver teraclock 1soe 2soe 1 q 0 1 q 1 2 q 0 2 q 1 3 q 0 3 q 1 4 q 0 4 q 1 5 q 0 5 q 1 q fb q fb divide select 1f 2:1 divide select 2f 2:1 divide select 3f 2:1 divide select 4f 2:1 divide select 5f 2:1 txs ref 0 ref 0 / v ref0 fb fb/ v ref2 rxs ref 1 ref 1 / v ref1 0 1 pll pd fs lock pe pll_en /n ds 1:0 3 3 ref_sel 0 1 divide select fbf 2:1 omode 3soe 4soe 5soe may 2003 2004 integrated device technology, inc. dsc 5981/24 c industrial temperature range the idt logo is a registered trademark of integrated device technology, inc. features: ? 2.5 v dd ? 5 pairs of outputs ? low skew: 50ps same pair, 100ps all outputs ? selectable positive or negative edge synchronization ? tolerant of spread spectrum input clock ? synchronous output enable ? selectable inputs ? input frequency: 4.17mhz to 250mhz ? output frequency: 12.5mhz to 250mhz ? 1.8v / 2.5v lvttl: up to 250mhz ? hstl / ehstl: up to 250mhz ? hot insertable and over-voltage tolerant inputs ? 3-level inputs for selectable interface ? 3-level inputs for feedback divide selection with multiply ratios of(1-6, 8, 10, 12) ? selectable hstl, ehstl, 1.8v/2.5v lvttl, or lvepecl input interface ? selectable differential or single-ended inputs and ten single- ended outputs ? pll bypass for dc testing ? external differential feedback, internal loop filter ? low jitter: <75ps cycle-to-cycle ? power-down mode ? lock indicator ? available in bga and vfqfpn packages functional block diagram IDT5T2010 2.5v zero delay pll clock driver teraclock? description: the IDT5T2010 is a 2.5v pll clock driver intended for high perfor- mance computing and data-communications applications. the IDT5T2010 has ten outputs in five banks of two, plus a dedicated differential feedback. the redundant input capability allows for a smooth change over to a secondary clock source when the primary clock source is absent. the feedback bank allows divide-by-functionality from 1 to 12 through the use of the ds[1:0] inputs. this provides the user with frequency multiplication 1 to 12 without using divided outputs for feedback. each output bank also allows for a divide-by functionality of 2 or 4. the IDT5T2010 features a user-selectable, single-ended or differential input to ten single-ended outputs. the clock driver also acts as a translator from a differential hstl, ehstl, 1.8v/2.5v lvttl, lvepecl, or single-ended 1.8v/2.5v lvttl input to hstl, ehstl, or 1.8v/2.5v lvttl outputs. selectable interface is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. the outputs can be synchronously enabled/disabled. furthermore, when pe is held high, all the outputs are synchronized with the positive edge of the ref clock input. when pe is held low, all the outputs are synchronized with the negative edge of ref.
2 industrial temperature range IDT5T2010 2.5v zero delay pll clock driver teraclock pin configuration a a 1f 2 v dd gnd 1soe 1 q 0 1 q 1 gnd 2 q 1 2 q 0 2soe 2f 2 v ddq b b v dd v dd 1f 1 gnd gnd 2f 1 v dd nc nc v ddq v ddq 3f 2 c c v dd omode v dd v dd gnd gnd gnd gnd v ddq v ddq d e f g h j k l m d e f g h j k l m 1 2 3 4 5 6 7 8 9 10 11 12 1 2 ref 1 /v ref1 ref 0 /v ref0 fb /v ref2 pll_ en gnd txs v dd v dd ds 0 34567 89101112 ref_ sel ref 1 pd rxs lock v dd ds 1 fb ref 0 nc 3f 1 v ddq v ddq 4f 1 nc 3 q 0 3 q 1 v ddq v ddq 4 q 1 4 q 0 fbf 1 gnd gnd 5f 1 fs fbf 2 v dd nc v dd v dd pe v dd v dd v dd v dd v dd v dd v dd v dd v dd nc qfb qfb gnd gnd 5 q 15 q 0 nc gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq 5f 2 4f 2 v ddq gnd v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq 3soe 4soe 5soe bga top view
3 industrial temperature range IDT5T2010 2.5v zero delay pll clock driver teraclock pin configuration vfqfpn top view 2 f 1 v d d q v d d 1 f 1 1 f 2 1 q 1 1 s o e v d d o m o d e 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 v d d q 2 f 2 2 q 0 2 s o e v d d q v d d q 2 q 1 5 8 5 7 5 6 5 5 5 4 5 3 5 2 1 q 0 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 v d d q f s f b f 2 q f b f b f 1 v d d q q f b v d d 1 8 1 9 d s 1 d s 0 2 8 2 9 3 0 3 1 3 2 3 3 3 4 5 q 0 5 f 1 5 q 1 5 s o e 5 f 2 v d d q v d d q 3 soe 3 f 2 v ddq v ddq 3 q 0 51 50 49 48 47 46 45 44 43 42 3 q 1 v dd 4 f 1 v dd 3 f 1 4 q 1 4 q 0 v ddq 41 40 39 38 37 36 35 v ddq 4 f 2 v dd 4 soe ref_sel v dd ref 1 fb ref 1 /v ref1 ref 0 ref 0 /v ref0 2 3 4 5 6 7 1 pe fb/v ref2 8 9 10 v dd pd pll_en v dd v dd rxs txs lock 12 13 14 15 16 17 11 gnd
4 industrial temperature range IDT5T2010 2.5v zero delay pll clock driver teraclock note: 1. capacitance applies to all inputs except rxs, txs, nf [2:1] , fbf [2:1] , and ds [1:0] . capacitance (t a = +25c, f = 1mhz, v in = 0v) parameter description min. typ. max. unit c in input capacitance 2.5 3 3.5 pf c out output capacitance ? 6.3 7 pf symbol description max unit v ddq , v dd power supply voltage (2) ?0.5 to +3.6 v v i input voltage ?0.5 to +3.6 v v o output voltage ?0.5 to v ddq +0.5 v v ref reference voltage (3) ?0.5 to +3.6 v t j junction temperature 150 c t stg storage temperature ?65 to +165 c absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v ddq and v dd internally operate independently. no power sequencing requirements need to be met. 3. not to exceed 3.6v. symbol description min. typ. max. unit t a ambient operating temperature ?40 +25 +85 c v dd (1) internal power supply voltage 2.3 2.5 2.7 v hstl output power supply voltage 1.4 1.5 1.6 v v ddq (1) extended hstl and 1.8v lvttl output power supply voltage 1.65 1.8 1.95 v 2.5v lvttl output power supply voltage v dd v v t termination voltage v ddq / 2 v recommended operating range note: 1. inputs are capable of translating the following interface standards. user can select between: single-ended 2.5v lvttl levels single-ended 1.8v lvttl levels or differential 2.5v/1.8v lvttl levels differential hstl and ehstl levels differential lvepecl levels pin description symbol i/o type description ref [1:0] i adjustable (1) clock input. ref [1:0] is the "true" side of the differential clock input. if operating in single-ended mode, ref [1:0] is the clock input. ref [1:0] / i adjustable (1) complementary clock input. ref [1:0] /v ref [1:0] is the "complementary" side of ref [1:0] if the input is in differential mode. if operating v ref [1:0] in single-ended mode, ref [1:0] /v ref [1:0] is left floating. for single-ended operation in differential mode, ref [1:0] /v ref [1:0] should be set to the desired toggle voltage for ref [1:0] : 2.5v lvttl v ref = 1250mv (sstl2 compatible) 1.8v lvttl, ehstl v ref = 900mv hstl v ref = 750mv lvepecl v ref = 1082mv fb i adjustable (1) clock input. fb is the "true" side of the differential feedback clock input. if operating in single-ended mode, fb is the fee dback clock input. fb /v ref 2 i adjustable (1) complementary feedback clock input. fb /v ref 2 is the "complementary" side of fb if the input is in differential mode. if operating in single- ended mode, fb /v ref 2 is left floating. for single-ended operation in differential mode, fb /v ref 2 should be set to the desired toggle voltage for fb: 2.5v lvttl v ref = 1250mv (sstl2 compatible) 1.8v lvttl, ehstl v ref = 900mv hstl v ref = 750mv lvepecl v ref = 1082mv note: 1. all power supplies should operate in tandem. if v dd or v ddq is at maximum, then v ddq or v dd (respectively) should be at maximum, and vice-versa.
5 industrial temperature range IDT5T2010 2.5v zero delay pll clock driver teraclock pin description, continued symbol i/o type description ref_sel i lvttl (1) reference clock select. when low, selects ref 0 and ref 0 /v ref 0. when high, selects ref 1 and ref 1 /v ref 1. nsoe i lvttl (1) synchronous output enable. when nsoe is high, nq [1:0] are synchronously stopped. omode selects whether the outputs are gated low/high or tri-stated. when omode is high, pe determines the level at which the outputs stop. when pe is low/high, the nq [1:0] is stopped in a high/low state. when omode is low, the outputs are tri-stated. set nsoe low for normal operation. qfb o adjustable (2) feedback clock output qfb o adjustable (2) complementary feedback clock output nq [1:0] o adjustable (2) five banks of two outputs rxs i 3-level (3) selects single-ended 2.5v lvttl (high), 1.8v lvttl (mid) ref clock input or differential (low) ref clock input txs i 3-level (3) sets the drive strength of the output drivers and feedback inputs to be 2.5v lvttl (high), 1.8v lvttl (mid) or hstl/ehstl (low) compatible. used in conjuction with v ddq to set the interface levels. p e i lvttl (1) selectable positive or negative edge control. when low/high the outputs are synchronized with the negative/positive edge of th e reference clock (has internal pull-up). nf [2:1] i lvttl (1) function select inputs for divide-by-2, divide-by-4, zero delay, or invert on each bank (see control summary table) fbf [2:1] i lvttl (1) function select inputs for divide-by-2, divide-by-4, zero delay, or invert on the feedback bank (see control summary table) fs i lvttl (1) selects appropriate oscillator circuit based on anticipated frequency range. (see vco frequency range select.) ds [1:0] i 3-level (3) 3-level inputs for feedback input divider selection (see divide selection table) pll_en i lvttl (1) pll enable/disable control. set low for normal operation. when pll_en is high, the pll is disabled and ref [1:0] goes to all outputs. pd i lvttl (1) power down control. when pd is low, the inputs are disabled and internal switching is stopped. omode selects whether the outputs are gated low/high or tri-stated. when omode is high, pe determines the level at which the outputs stop. when pe is low/ high, the nq [1:0] and qfb are stopped in a high/low state, while the qfb is stopped in a low/high state. when omode is low, the outputs are tri-stated. set pd high for normal operation. lock o lvttl pll lock indication signal. high indicates lock. low indicates that the pll is not locked and outputs may not be synchronized to the inputs. the output will be 2.5v lvttl. omode i lvttl (1) output disable control. determines the outputs' disable state. used in conjunction with nsoe and pd . (see output enable/disable and powerdown tables.) v ddq pwr power supply for output buffers. when using 2.5v lvttl, v ddq should be connected to v dd. v dd pwr power supply for phase locked loop, lock output, inputs, and other internal circuitry gnd pwr ground notes: 1. pins listed as lvttl inputs will accept 2.5v signals under all conditions. if the output is operating at 1.8v or 1.5v, the l vttl inputs will accept 1.8v lvttl signals as well. 2. outputs are user selectable to drive 2.5v, 1.8v lvttl, ehstl, or hstl interface levels when used with the appropriate v ddq voltage. 3. 3-level inputs are static inputs and must be tied to v dd or gnd or left floating. these inputs are not hot-insertable or over voltage tolerant. note: 1. the level to be set on fs is determined by the nominal operating frequency of the vco. the vco frequency (f nom ) always appears at nq [1:0] outputs when they are operated in their undivided modes. the frequency appearing at the ref [1:0] and ref [1:0] /v ref [1:0] and fb and fb /v ref 2 inputs will be f nom when the qfb and qfb are undivided and ds [1:0] = mm. the frequency of ref [1:0] and ref [1:0] /v ref [1:0] and fb and fb /v ref 2 inputs will be f nom /2 or f nom /4 when the part is configured for frequency multiplication by using a divided qfb and qfb and setting ds [1:0] = mm. using the ds [1:0] inputs allows a different method for frequency multiplication (see divide selection table). vco frequency range select fs (1) min. max. unit low 50 125 mhz high 100 250 mhz note: 1. pe determines the level at which the outputs stop. when pe is low/high, the nq [1:0] is stopped in a high/low state. output enable/disable nsoe omode output l x normal operation h l tri-state h h gated (1) note: 1. pe determines the level at which the outputs stop. when pe is low/high, the nq [1:0] and qfb are stopped in a high/low state, while the qfb is stopped in a low/high state. powerdown pd omode output h x normal operation l l tri-state l h gated (1)
6 industrial temperature range IDT5T2010 2.5v zero delay pll clock driver teraclock external differential feedback by providing a dedicated external differential feedback, the IDT5T2010 gives users flexibility with regard to divide selection. the fb and fb / v ref2 signals are compared with the input ref [1:0] and ref [1:0] /v ref[1:0] signals at the phase detector in order to drive the vco. phase differ- ences cause the vco of the pll to adjust upwards or downwards accordingly. an internal loop filter moderates the response of the vco to the phase detector. the loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accu- rate responses to input frequency changes. divide selection table ds [ 1:0 ] divide-by-n permitted output divide-by-n connected to fb and fb /v ref2 (1) ll 2 1, 2 lm 3 1 lh 4 1, 2 ml 5 1, 2 m m 1 1, 2, 4 m h 6 1, 2 hl 8 1 hm 10 1 hh 12 1 note: 1. permissible output division ratios connected to fb and fb /v ref 2 . the frequencies of the ref [1:0] and ref [1:0] /v ref [1:0] inputs will be f nom /n when the parts are configured for frequency multiplication by using an undivided output for fb and fb /v ref 2 and setting ds[ 1:0 ] to n (n = 1-6, 8, 10, 12). control summary table for all outputs nf 2 /fbf 2 nf 1 /fbf 1 output skew l l divide by 2 l h zero delay h l inverted h h divide by 4
7 industrial temperature range IDT5T2010 2.5v zero delay pll clock driver teraclock input/output selection (1) input output 2.5v lvttl se 2.5v lvttl 1.8v lvttl se 2.5v lvttl dse 1.8v lvttl dse lvepecl dse ehstl dse hstl dse 2.5v lvttl dif 1.8v lvttl dif lvepecl dif ehstl dif hstl dif 2.5v lvttl se 1.8v lvttl 1.8v lvttl se 2.5v lvttl dse 1.8v lvttl dse lvepecl dse ehstl dse hstl dse 2.5v lvttl dif 1.8v lvttl dif lvepecl dif ehstl dif hstl dif input output 2.5v lvttl se ehstl 1.8v lvttl se 2.5v lvttl dse 1.8v lvttl dse lvepecl dse ehstl dse hstl dse 2.5v lvttl dif 1.8v lvttl dif lvepecl dif ehstl dif hstl dif 2.5v lvttl se hstl 1.8v lvttl se 2.5v lvttl dse 1.8v lvttl dse lvepecl dse ehstl dse hstl dse 2.5v lvttl dif 1.8v lvttl dif lvepecl dif ehstl dif hstl dif note: 1. the input/output selection table describes the total possible combinations of input and output interfaces. single-ended (se) inputs in a single-ended mode require the ref [1:0] /v ref [1:0] and fb /v ref 2 pins to be left floating. differential single-ended (dse) is for single-ended operation in differential mode, requiring v ref [1:0] and v ref 2 . differential (dif) inputs are used only in differential mode. note: 1. these inputs are normally wired to v dd , gnd, or left floating. internal termination resistors bias unconnected inputs to v dd /2. if these inputs are switched dynamically after powerup, the function and timing of the outputs may be glitched, and the pll may require additional t lock time before all datasheet limits are achieved. dc electrical characteristics over operating range symbol parameter test conditions min. max unit v ihh input high voltage level (1) 3-level inputs only v dd ? 0.4 ? v v imm input mid voltage level (1) 3-level inputs only v dd /2 ? 0.2 v dd /2 + 0.2 v v ill input low voltage level (1) 3-level inputs only ? 0.4 v v in = v dd high level ? 200 i 3 3-level input dc current v in = v dd /2 mid level ?50 +50 a (rxs, txs, ds [1:0] )v in = gnd low level ?200 ? i pu input pull-up current (pe) v dd = max., v in = gnd ?100 ? a
8 industrial temperature range IDT5T2010 2.5v zero delay pll clock driver teraclock dc electrical characteristics over operating range for hstl (1) symbol parameter test conditions min. typ. (7) max unit input characteristics i ih input high current v dd = 2.7v v i = v ddq /gnd ? ? 5 a i il input low current v dd = 2.7v v i = gnd/v ddq ??5 v ik clamp diode voltage v dd = 2.3v, i in = -18ma ? - 0.7 - 1.2 v v in dc input voltage - 0.3 +3.6 v v dif dc differential voltage (2,8) 0.2 ? v v cm dc common mode input voltage (3,8) 680 750 900 mv v ih dc input high (4,5,8) v ref + 100 ? mv v il dc input low (4,6,8) ?v ref - 100 mv v ref single-ended reference voltage (4,8) ? 750 ? mv output characteristics v oh output high voltage i oh = -8ma v ddq - 0.4 ? v i oh = -100 av ddq - 0.1 ? v ol output low voltage i ol = 8ma ? 0.4 v i ol = 100 a ? 0.1 v ox fb/ fb output crossing point v ddq /2 - 150 v ddq /2 v ddq /2 + 150 mv notes: 1. see recommended operating range table. 2. v dif specifies the minimum input differential voltage (v tr - v cp ) required for switching where v tr is the "true" input level and v cp is the "complement" input level. differential mode only. the dc differential voltage must be maintained to guarantee retaining the existing high or low input. the ac differenti al voltage must be achieved to guarantee switching to a new state. 3. v cm specifies the maximum allowable range of (v tr + v cp ) /2. differential mode only. 4. for single-ended operation, in differential mode, ref [1:0] /v ref [1:0] is tied to the dc voltage v ref [1:0] . 5. voltage required to maintain a logic high, single-ended operation in differential mode. 6. voltage required to maintain a logic low, single-ended operation in differential mode. 7. typical values are at v dd = 2.5v, v ddq = 1.5v, +25c ambient. 8. the reference clock input is capable of hstl, ehstl, lvepecl, 1.8v or 2.5v lvttl operation independent of the device output. (see input/output selection table.) power supply characteristics for hstl outputs (1) symbol parameter test conditions (2) typ. max unit i ddq quiescent v dd power supply current (3) v ddq = max., ref = low, pd = high, nsoe = low, 15 25 ma pll_en = high, ds [1:0] = mm, nf [2:1] = lh, fbf [2:1] = lh, outputs enabled, all outputs unloaded i ddqq quiescent v ddq power supply current (3) v ddq = max., ref = low, pd = high, nsoe = low, 0.7 50 a pll_en = high, ds [1:0] = mm, nf [2:1] = lh, fbf [2:1] = lh, outputs enabled, all outputs unloaded i ddpd power down current v dd = max., pd = low, nsoe = low, pll_en = high 0.8 3 ma i ddd dynamic v dd power supply v dd = max., v ddq = max., c l = 0pf 13 20 a/mhz current per output i dddq dynamic v ddq power supply v dd = max., v ddq = max., c l = 0pf 16 25 a/mhz current per output i tot total power v dd supply current (4) v ddq = 1.5v, f vco = 100mhz, c l = 15pf 35 55 ma v ddq = 1.5v, f vco = 250mhz, c l = 15pf 55 85 i totq total power v ddq supply current (4) v ddq = 1.5v, f vco = 100mhz, c l = 15pf 45 70 ma v ddq = 1.5v, f vco = 250mhz, c l = 15pf 80 120 notes: 1. these power consumption characteristics are for all the valid input interfaces and cover the worst case input and output inte rface combinations. 2. the termination resistors are excluded from these measurements. 3. if the differential input interface is used, the true input is held low and the complementary input is held high. 4. fs = high.
9 industrial temperature range IDT5T2010 2.5v zero delay pll clock driver teraclock differential input ac test conditions for hstl symbol parameter value units v dif input signal swing (1) 1v v x differential input signal crossing point (2) 750 mv v thi input timing measurement reference level (3) crossing point v t r , t f input signal edge rate (4) 1 v/ns notes: 1. the 1v peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (at e) environment. this device meets the v dif (ac) specification under actual use conditions. 2. a 750mv crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ate) envir onment. this device meets the v x specification under actual use conditions. 3. in all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. the input signal edge rate of 1v/ns or greater is to be maintained in the 20% to 80% range of the input waveform. dc electrical characteristics over operating range for ehstl (1) symbol parameter test conditions min. typ. (7) max unit input characteristics i ih input high current v dd = 2.7v v i = v ddq /gnd ? ? 5 a i il input low current v dd = 2.7v v i = gnd/v ddq ??5 v ik clamp diode voltage v dd = 2.3v, i in = -18ma ? - 0.7 - 1.2 v v in dc input voltage - 0.3 +3.6 v v dif dc differential voltage (2,8) 0.2 ? v v cm dc common mode input voltage (3,8) 800 900 1000 mv v ih dc input high (4,5,8) v ref + 100 ? mv v il dc input low (4,6,8) ?v ref - 100 mv v ref single-ended reference voltage (4,8) ? 900 ? mv output characteristics v oh output high voltage i oh = -8ma v ddq - 0.4 ? v i oh = -100 av ddq - 0.1 ? v v ol output low voltage i ol = 8ma ? 0.4 v i ol = 100 a ? 0.1 v v ox fb/ fb output crossing point v ddq /2 - 150 v ddq /2 v ddq /2 + 150 mv notes: 1. see recommended operating range table. 2. v dif specifies the minimum input differential voltage (v tr - v cp ) required for switching where v tr is the "true" input level and v cp is the "complement" input level. differential mode only. the dc differential voltage must be maintained to guarantee retaining the existing high or low input. the ac differenti al voltage must be achieved to guarantee switching to a new state. 3. v cm specifies the maximum allowable range of (v tr + v cp ) /2. differential mode only. 4. for single-ended operation, in a differential mode, ref [1:0] /v ref [1:0] is tied to the dc voltage v ref [1:0] . 5. voltage required to maintain a logic high, single-ended operation in differential mode. 6. voltage required to maintain a logic low, single-ended operation in differential mode. 7. typical values are at v dd = 2.5v, v ddq = 1.8v, +25c ambient. 8. the reference clock input is capable of hstl, ehstl, lvepecl, 1.8v or 2.5v lvttl operation independent of the device output. (see input/output selection table.)
10 industrial temperature range IDT5T2010 2.5v zero delay pll clock driver teraclock differential input ac test conditions for ehstl symbol parameter value units v dif input signal swing (1) 1v v x differential input signal crossing point (2) 900 mv v thi input timing measurement reference level (3) crossing point v t r , t f input signal edge rate (4) 1 v/ns notes: 1. the 1v peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (at e) environment. this device meets the v dif (ac) specification under actual use conditions. 2. a 900mv crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ate) envir onment. this device meets the v x specification under actual use conditions. 3. in all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. the input signal edge rate of 1v/ns or greater is to be maintained in the 20% to 80% range of the input waveform. power supply characteristics for ehstl outputs (1) symbol parameter test conditions (2) typ. max unit i ddq quiescent v dd power supply current (3) v ddq = max., ref = low, pd = high, nsoe = low, 15 25 ma pll_en = high, ds [1:0] = mm, nf [2:1] = lh, fbf [2:1] = lh, outputs enabled, all outputs unloaded i ddqq quiescent v ddq power supply current (3) v ddq = max., ref = low, pd = high, nsoe = low, 1.7 50 a pll_en = high, ds [1:0] = mm, nf [2:1] = lh, fbf [2:1] = lh, outputs enabled, all outputs unloaded i ddpd power down current v dd = max., pd = low, nsoe = low, pll_en = high 0.8 3 ma i ddd dynamic v dd power supply v dd = max., v ddq = max., c l = 0pf 13 20 a/mhz current per output i dddq dynamic v ddq power supply v dd = max., v ddq = max., c l = 0pf 20 30 a/mhz current per output i tot total power v dd supply current (4) v ddq = 1.8v, f vco = 100mhz, c l = 15pf 35 55 ma v ddq = 1.8v, f vco = 250mhz, c l = 15pf 55 85 i totq total power v ddq supply current (4) v ddq = 1.8v, f vco = 100mhz, c l = 15pf 50 75 ma v ddq = 1.8v, f vco = 250mhz, c l = 15pf 115 175 notes: 1. these power consumption characteristics are for all the valid input interfaces and cover the worst case input and output inte rface combinations. 2. the termination resistors are excluded from these measurements. 3. if the differential input interface is used, the true input is held low and the complementary input is held high. 4. fs = high.
11 industrial temperature range IDT5T2010 2.5v zero delay pll clock driver teraclock dc electrical characteristics over operating range for lvepecl (1) symbol parameter test conditions min. typ. (2) max unit input characteristics i ih input high current v dd = 2.7v v i = v ddq /gnd ? ? 5 a i il input low current v dd = 2.7v v i = gnd/v ddq ??5 v ik clamp diode voltage v dd = 2.3v, i in = -18ma ? - 0.7 - 1.2 v v in dc input voltage - 0.3 ? 3.6 v v cm dc common mode input voltage (3,5) 915 1082 1248 mv v ref single-ended reference voltage (4,5) ? 1082 ? mv v ih dc input high 1275 ? 1620 mv v il dc input low 555 ? 875 mv notes: 1. see recommended operating range table. 2. typical values are at v dd = 2.5v, +25c ambient. 3. v cm specifies the maximum allowable range of (v tr + v cp ) /2. differential mode only. 4. for single-ended operation while in differential mode, ref [1:0] /v ref [1:0] is tied to the dc voltage v ref [1:0] . 5. the reference clock input is capable of hstl, ehstl, lvepecl, 1.8v or 2.5v lvttl operation independent of the device output. (see input/output selection table.) differential input ac test conditions for lvepecl symbol parameter value units v dif input signal swing (1) 732 mv v x differential input signal crossing point (2) 1082 mv v thi input timing measurement reference level (3) crossing point v t r , t f input signal edge rate (4) 1 v/ns notes: 1. the 732mv peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ate) environment. this device meets the v dif (ac) specification under actual use conditions. 2. a 1082mv crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ate) envi ronment. this device meets the v x specification under actual use conditions. 3. in all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. the input signal edge rate of 1v/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
12 industrial temperature range IDT5T2010 2.5v zero delay pll clock driver teraclock notes: 1. see recommended operating range table. 2. for 2.5v lvttl single-ended operation, the rxs pin is tied high and ref [1:0] /v ref [1:0] is left floating. if txs is high, fb /v ref 2 should be left floating. 3. v dif specifies the minimum input differential voltage (v tr - v cp ) required for switching where v tr is the "true" input level and v cp is the "complement" input level. differential mode only. the dc differential voltage must be maintained to guarantee retaining the existing high or low input. the ac differenti al voltage must be achieved to guarantee switching to a new state. 4. v cm specifies the maximum allowable range of (v tr + v cp ) /2. differential mode only. 5. for single-ended operation, in differential mode, ref [1:0] /v ref [1:0] is tied to the dc voltage v ref [1:0] . 6. voltage required to maintain a logic high, single-ended operation in differential mode. 7. voltage required to maintain a logic low, single-ended operation in differential mode. 8. typical values are at v dd = 2.5v, v ddq = v dd , +25c ambient. 9. the reference clock input is capable of hstl, ehstl, lvepecl, 1.8v or 2.5v lvttl operation independent of the device output. (see input/output selection table.) dc electrical characteristics over operating range for 2.5v lvttl (1) symbol parameter test conditions min. typ. (8) max unit input characteristics i ih input high current v dd = 2.7v v i = v ddq /gnd ? ? 5 a i il input low current v dd = 2.7v v i = gnd/v ddq ??5 v ik clamp diode voltage v dd = 2.3v, i in = -18ma ? - 0.7 - 1.2 v v in dc input voltage - 0.3 +3.6 v single-ended inputs (2) v ih dc input high 1.7 ? v v il dc input low ? 0.7 v differential inputs v dif dc differential voltage (3,9) 0.2 ? v v cm dc common mode input voltage (4,9) 1150 1250 1350 mv v ih dc input high (5,6,9) v ref + 100 ? mv v il dc input low (5,7,9) ?v ref - 100 mv v ref single-ended reference voltage (5,9) ? 1250 ? mv output characteristics v oh output high voltage i oh = -12ma v ddq - 0.4 ? v i oh = -100 av ddq - 0.1 ? v v ol output low voltage i ol = 12ma ? 0.4 v i ol = 100 a ? 0.1 v
13 industrial temperature range IDT5T2010 2.5v zero delay pll clock driver teraclock single-ended input ac test conditions for 2.5v lvttl symbol parameter value units v ih input high voltage v dd v v il input low voltage 0v v thi input timing measurement reference level (1) v dd /2 v t r , t f input signal edge rate (2) 2 v/ns notes: 1. a nominal 1.25v timing measurement reference level is specified to allow constant, repeatable results in an automatic test eq uipment (ate) environment. 2. the input signal edge rate of 2v/ns or greater is to be maintained in the 10% to 90% range of the input waveform. differential input ac test conditions for 2.5v lvttl symbol parameter value units v dif input signal swing (1) v dd v v x differential input signal crossing point (2) v dd /2 v v thi input timing measurement reference level (3) crossing point v t r , t f input signal edge rate (4) 2.5 v/ns notes: 1. a nominal 2.5v peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equip ment (ate) environment. this device meets the v dif (ac) specification under actual use conditions. 2. a nominal 1.25v crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ate ) environment. this device meets the v x specification under actual use conditions. 3. in all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. the input signal edge rate of 2.5v/ns or greater is to be maintained in the 20% to 80% range of the input waveform. power supply characteristics for 2.5v lvttl outputs (1) symbol parameter test conditions (2) typ. max unit i ddq quiescent v dd power supply current (3) v ddq = max., ref = low, pd = high, nsoe = low, 15 25 ma pll_en = high, ds [1:0] = mm, nf [2:1] = lh, fbf [2:1] = lh, outputs enabled, all outputs unloaded i ddqq quiescent v ddq power supply current (3) v ddq = max., ref = low, pd = high, nsoe = low, 12 50 a pll_en = high, ds [1:0] = mm, nf [2:1] = lh, fbf [2:1] = lh, outputs enabled, all outputs unloaded i ddpd power down current v dd = max., pd = low, nsoe = low, pll_en = high 0.5 3 ma i ddd dynamic v dd power supply v dd = max., v ddq = max., c l = 0pf 15 25 a/mhz current per output i dddq dynamic v ddq power supply v dd = max., v ddq = max., c l = 0pf 30 40 a/mhz current per output i tot total power v dd supply current (4) v ddq = 2.5v., f vco = 100mhz, c l = 15pf 40 60 ma v ddq = 2.5v., f vco = 250mhz, c l = 15pf 60 90 i totq total power v ddq supply current (4) v ddq = 2.5v., f vco = 100mhz, c l = 15pf 80 120 ma v ddq = 2.5v., f vco = 250mhz, c l = 15pf 200 300 notes: 1. these power consumption characteristics are for all the valid input interfaces and cover the worst case input and output inte rface combinations. 2. the termination resistors are excluded from these measurements. 3. if the differential input interface is used, the true input is held low and the complementary input is held high. 4. fs = high.
14 industrial temperature range IDT5T2010 2.5v zero delay pll clock driver teraclock notes: 1. see recommended operating range table. 2. for 1.8v lvttl single-ended operation, the rxs pin is mid and ref [1:0] /v ref [1:0] is left floating. if txs is mid, fb /v ref 2 should be left floating. 3. v dif specifies the minimum input differential voltage (v tr - v cp ) required for switching where v tr is the "true" input level and v cp is the "complement" input level. differential mode only. the dc differential voltage must be maintained to guarantee retaining the existing high or low input. the ac differenti al voltage must be achieved to guarantee switching to a new state. 4. v cm specifies the maximum allowable range of (v tr + v cp ) /2. differential mode only. 5. for single-ended operation in differential mode, ref [1:0] /v ref [1:0] is tied to the dc voltage v ref [1:0] . the input is guaranteed to toggle within 200mv of v ref [1:0] when v ref [1:0] is constrained within +600mv and v ddi -600mv, where v ddi is the nominal 1.8v power supply of the device driving the ref [1:0] input. to guarantee switching in voltage range specified in the jedec 1.8v lvttl interface specification, v ref [1:0] must be maintained at 900mv with appropriate tolerances. 6. voltage required to maintain a logic high, single-ended operation in differential mode. 7. voltage required to maintain a logic low, single-ended operation in differential mode. 8. typical values are at v dd = 2.5v, v ddq = 1.8v, +25c ambient. 9. the reference clock input is capable of hstl, ehstl, lvepecl, 1.8v or 2.5v lvttl operation independent of the device output. (see input/output selection table.) 10. this value is the worst case minimum v ih over the specification range of the 1.8v power supply. the 1.8v lvttl specification is v ih = 0.65 * v dd where v dd is 1.8v 0.15v. however, the lvttl translator is supplied by a 2.5v nominal supply on this part. to ensure compliance with the specification, the translator was designed to accept the calculated worst case value ( v ih = 0.65 * [1.8 - 0.15v]) rather than reference against a nominal 1.8v supply. 11. this value is the worst case maximum v il over the specification range of the 1.8v power supply. the 1.8v lvttl specification is v il = 0.35 * v dd where v dd is 1.8v 0.15v. however, the lvttl translator is supplied by a 2.5v nominal supply on this part. to ensure compliance with the specification, the translator was designed to accept the calculated worst case value ( v il = 0.35 * [1.8 + 0.15v]) rather than reference against a nominal 1.8v supply. dc electrical characteristics over operating range for 1.8v lvttl (1) symbol parameter test conditions min. typ. (8) max unit input characteristics i ih input high current v dd = 2.7v v i = v ddq /gnd ? ? 5 a i il input low current v dd = 2.7v v i = gnd/v ddq ??5 v ik clamp diode voltage v dd = 2.3v, i in = -18ma ? - 0.7 - 1.2 v v in dc input voltage - 0.3 v ddq + 0.3 v single-ended inputs (2) v ih dc input high 1.073 (10) ?v v il dc input low ? 0.683 (11) v differential inputs v dif dc differential voltage (3,9) 0.2 ? v v cm dc common mode input voltage (4,9) 825 900 975 mv v ih dc input high (5,6,9) v ref + 100 ? mv v il dc input low (5,7,9) ?v ref - 100 mv v ref single-ended reference voltage (5,9) ? 900 ? mv output characteristics v oh output high voltage i oh = -6ma v ddq - 0.4 ? v i oh = -100 av ddq - 0.1 ? v v ol output low voltage i ol = 6ma ? 0.4 v i ol = 100 a ? 0.1 v
15 industrial temperature range IDT5T2010 2.5v zero delay pll clock driver teraclock single-ended input ac test conditions for 1.8v lvttl symbol parameter value units v ih input high voltage (1) v ddi v v il input low voltage 0v v thi input timing measurement reference level (2) v ddi /2 mv t r , t f input signal edge rate (3) 2 v/ns notes: 1. v ddi is the nominal 1.8v supply (1.8v 0.15v) of the part or source driving the input. 2. a nominal 900mv timing measurement reference level is specified to allow constant, repeatable results in an automatic test eq uipment (ate) environment. 3. the input signal edge rate of 2v/ns or greater is to be maintained in the 10% to 90% range of the input waveform. differential input ac test conditions for 1.8v lvttl symbol parameter value units v dif input signal swing (1) v ddi v v x differential input signal crossing point (2) v ddi /2 mv v thi input timing measurement reference level (3) crossing point v t r , t f input signal edge rate (4) 1.8 v/ns notes: 1. v ddi is the nominal 1.8v supply (1.8v 0.15v) of the part or source driving the input. a nominal 1.8v peak-to-peak input pulse le vel is specified to allow consistent, repeatable results in an automatic test equipment (ate) environment. this device meets the v dif (ac) specification under actual use conditions. 2. a nominal 900mv crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ate ) environment. this device meets the v x specification under actual use conditions. 3. in all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. the input signal edge rate of 1.8v/ns or greater is to be maintained in the 20% to 80% range of the input waveform. power supply characteristics for 1.8v lvttl outputs (1) symbol parameter test conditions (2) typ. max unit i ddq quiescent v dd power supply current (3) v ddq = max., ref = low, pd = high, nsoe = low, 15 25 ma pll_en = high, ds [1:0] = mm, nf [2:1] = lh, fbf [2:1] = lh, outputs enabled, all outputs unloaded i ddqq quiescent v ddq power supply current (3) v ddq = max., ref = low, pd = high, nsoe = low, 1.5 50 a pll_en = high, ds [1:0] = mm, nf [2:1] = lh, fbf [2:1] = lh, outputs enabled, all outputs unloaded i ddpd power down current v dd = max., pd = low, nsoe = low, pll_en = high 0.5 3 ma i ddd dynamic v dd power supply v dd = max., v ddq = max., c l = 0pf 16 25 a/mhz current per output i dddq dynamic v ddq power supply v dd = max., v ddq = max., c l = 0pf 22 30 a/mhz current per output i tot total power v dd supply current (4) v ddq = 1.8v., f vco = 100mhz, c l = 15pf 40 60 ma v ddq = 1.8v., f vco = 250mhz, c l = 15pf 70 105 i totq total power v ddq supply current (4) v ddq = 1.8v., f vco = 100mhz, c l = 15pf 55 85 ma v ddq = 1.8v., f vco = 250mhz, c l = 15pf 135 205 notes: 1. these power consumption characteristics are for all the valid input interfaces and cover the worst case input and output inte rface combinations. 2. the termination resistors are excluded from these measurements. 3. if the differential input interface is used, the true input is held low and the complementary input is held high. 4. fs = high.
16 industrial temperature range IDT5T2010 2.5v zero delay pll clock driver teraclock ac electrical characteristics over operating range symbol parameter min. typ. max unit f nom vco frequency range see vco frequency range select table t rpw reference clock pulse width high or low 1 ? ? ns t fpw feedback input pulse width high or low 1 ? ? ns t sk ( b ) output matched pair skew (1,2,4) ??50ps t sk ( o ) output skew (rise-rise, fall-fall, nominal) (1,3) ? ? 100 ps t sk 1 ( ) multiple frequency skew (rise-rise, fall-fall, nominal-divided, divided-divided) (1,3,4) ? ? 100 ps t sk 2 ( ) multiple frequency skew (rise-fall, nominal-divided, divided-divided) (1,3,4) ? ? 400 ps t sk 1 ( inv ) inverting skew (nominal-inverted) (1,3) ?? 400 ps t sk 2 ( inv ) inverting skew (rise-rise, fall-fall, rise-fall, inverted-divided) (1,3,4) ? ? 400 ps t sk ( pr ) process skew (1,3.5) ?? 300 ps t( ) ref input to fb static phase offset (6) -100 ? 100 ps t odcv output duty cycle variation from 50% (7) hstl / ehstl / 1.8v lvttl -375 ? 375 ps 2.5v lvttl -275 ? 275 t orise output rise time (8) hstl / ehstl / 1.8v lvttl ? ? 1.2 ns 2.5v lvttl ? ? 1 t ofall output fall time (8) hstl / ehstl / 1.8v lvttl ? ? 1.2 ns 2.5v lvttl ? ? 1 t l power-up pll lock time (9) ?? 1ms t l ( ) pll lock time after input frequency change (9) ?? 1ms t l ( refsel 1 ) pll lock time after change in ref_sel (9,11) ? ? 100 s t l ( refsel 2 ) pll lock time after change in ref_sel (ref 1 and ref 0 are different frequency) (9) ?? 1ms t l ( pd ) pll lock time after asserting pd pin (9) ?? 1ms t jit ( cc ) cycle-to-cycle output jitter (peak-to-peak) (10) ? 50 75 ps t jit ( per ) period jitter (peak-to-peak) (10) ?? 75 ps t jit ( hp ) half period jitter (peak-to-peak, qfb/ qfb only) (10, 12) ? ? 125 ps t jit ( duty ) duty cycle jitter (peak-to-peak) (10) ?? 100 ps v ox hstl and ehstl differential true and complementary output crossing voltage level v ddq /2 - 150 v ddq /2 v ddq /2 + 150 mv qfb/ qfb only (12) notes: 1. skew is the time between the earliest and latest output transition among all outputs when all outputs are loaded with the spe cified load. 2. t sk ( b ) is the skew between a pair of outputs (nq0 and nq1) when all outputs are selected as the same class. 3. the measurement is made at v ddq /2. 4. there are three classes of outputs: nominal (zero delay), inverted, and divided (divide-by-2 or divide-by-4 mode). 5. t sk ( pr ) is the output to corresponding output skew between any two devices operating under the same conditions (v dd and v ddq , ambient temperature, air flow, etc.). 6. t( ) is measured with ref and fb the same type of input, the same rise and fall times. for txs/rxs = mid or high, the measurement is taken from v thi on ref to v thi on fb. for txs/rxs = low, the measurement is taken from the crosspoint of ref/ ref to the crosspoint of fb/ fb . all outputs are set to zero delay, fb input divider set to divide- by-one, and fs = high. 7. t odcv is measured with all outputs selected for zero delay. 8. output rise and fall times are measured between 20% to 80% of the actual output voltage swing. 9. t l , t l ( ), t l ( refsel 1 ), t l ( refsel 2 ), and t l ( pd ) are the times that are required before the synchronization is achieved. these specifications are valid only after v dd /v ddq is stable and within the normal operating limits. these parameters are measured from the application of a new signal at ref or fb, or after pd is (re)asserted until t( ) is within specified limits. 10. the jitter parameters are measured with all outputs selected for zero delay, fb input divider is set to divide-by-one, and f s = high. 11. both ref inputs must be the same frequency, but up to 180 out of phase. 12. for hstl/ehstl outputs only.
17 industrial temperature range IDT5T2010 2.5v zero delay pll clock driver teraclock ac differential input specifications (1) symbol parameter min. typ. max unit t w reference/feedback input clock pulse width high or low (hstl/ehstl outputs) (2) 1??ns reference/feedback input clock pulse width high or low (2.5v / 1.8v lvttl outputs) (2) 1?? hstl/ehstl/1.8v lvttl/2.5v lvttl v dif ac differential voltage (3) 400 ? ? mv v ih ac input high (4,5) vx + 200 ? ? mv v il ac input low (4,6) ? ? vx - 200 mv lvepecl v dif ac differential voltage (3) 400 ? ? mv v ih ac input high (4) 1275 ? ? mv v il ac input low (4) ? ? 875 mv notes: 1. for differential input mode, rxs is tied to gnd. 2. both differential input signals should not be driven to the same level simultaneously. the input will not change state until the inputs have crossed and the voltage range defined by v dif has been met or exceeded. 3. differential mode only. v dif specifies the minimum input voltage (v tr - v cp ) required for switching where v tr is the "true" input level and v cp is the "complement" input level. the ac differential voltage must be achieved to guarantee switching to a new state. 4. for single-ended operation, ref [1:0] /v ref [1:0] is tied to the dc voltage v ref [1:0] . refer to each input interface's dc specification for the correct v ref [1:0] range. 5. voltage required to switch to a logic high, single-ended operation only. 6. voltage required to switch to a logic low, single-ended operation only.
18 industrial temperature range IDT5T2010 2.5v zero delay pll clock driver teraclock ac timing diagram (1) ref fb q other q inverted q q divided by 2 q divided by 4 t odcv t odcv t rpwh t rpwl ref fb t fpwh t sk1(inv) t sk2( ), t sk2(inv) t sk1( ), t sk2(inv) t sk1( ) t sk2( ) t sk2(inv) t sk1(inv) t sk(o), t sk(b) t sk(o), t sk(b) t fpwl t odcv t odcv note: 1. the ac timing diagram applies to pe = v dd . for pe = gnd, the negative edge of fb aligns with the negative edge of ref [1:0] , divided outputs change on the negative edge of ref [1:0] , and the positive edges of the divide-by-2 and divide-by-4 signals align.
19 industrial temperature range IDT5T2010 2.5v zero delay pll clock driver teraclock duty-cycle jitter nq [1:0] , q fb q fb t w(min) t w(max) t jit(duty) = t w(max) - t w(min) jitter and offset timing waveforms t cycle n t cycle n + 1 q fb t jit(cc) t cycle n t cycle n+1 = nq [1:0] , q fb cycle-to-cycle jitter static phase offset fb ref [1:0] t (?)n ref [1:0] fb t (?)n + 1 t (?) = n n = n 1 t (?)n (n is a large number of samples) note: 1. diagram for pe = h and txs/rxs = l.
20 industrial temperature range IDT5T2010 2.5v zero delay pll clock driver teraclock period jitter q fb q fb t cycle n 1 f o nq [1:0] , q fb nq [1:0] , q fb t jit(per) = t cycle n f o 1 1 f o t half period n t half period n+1 q fb q fb q fb q fb t jit(hper) = t half period n 2f o 1 * half-period jitter note: 1. 1/fo = average period. note: 1. 1/fo = average period.
21 industrial temperature range IDT5T2010 2.5v zero delay pll clock driver teraclock test circuits and conditions test circuit for differential input (1) v dd v ddq d.u.t. ref [1:0] ref [1:0] pulse generator 3 inch, ~50 ? transmission line 3 inch, ~50 ? transmission line v in v in v ddi r1 r2 v ddi r1 r2 differential input test conditions symbol v dd = 2.5v 0.2v unit r1 100 ? r2 100 ? v ddi v cm *2 v hstl: crossing of ref [1:0] and ref [1:0] ehstl: crossing of ref [1:0] and ref [1:0] v thi lvepecl: crossing of ref [1:0] and ref [1:0] v 1.8v lvttl: v ddi /2 2.5v lvttl: v dd /2 note: 1. this input configuration is used for all input interfaces. for single-ended testing, the ref [1:0] must be left floating. for testing single-ended in differential input mode, the v in should be floating.
22 industrial temperature range IDT5T2010 2.5v zero delay pll clock driver teraclock v dd v ddq d.u.t. q fb q fb c l v ddq r1 r2 v ddq r1 r2 c l ref [1:0] fb fb sw1 test circuit for outputs test circuit for differential feedback output test conditions symbol v dd = 2.5v 0.2v unit v ddq = interface specified c l 15 pf r1 100 ? r2 100 ? v tho v ddq / 2 v sw1 txs = mid or high open txs = low closed differential feedback test conditions symbol v dd = 2.5v 0.2v unit v ddq = interface specified c l 15 pf r1 100 ? r2 100 ? v ox hstl: crossing of q fb and q fb v ehstl: crossing of q fb and q fb v tho 1.8v lvttl: v ddq /2 v 2.5v lvttl: v ddq /2 sw1 txs = mid or high open txs = low closed v dd v ddq d.u.t. c l v ddq r1 r2 nq [1:0] ref [1:0] fb fb qfb qfb sw1
23 industrial temperature range IDT5T2010 2.5v zero delay pll clock driver teraclock ordering information idt xxxxx xx package device type 5t2010 2.5v zero delay pll clock driver teraclock plastic ball grid array thermally enhanced plastic very fine pitch quad flat no lead package bb nl package x -40c to +85c (industrial) i corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com

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